A semiconductor device disclosed in Japanese Patent Application Publication No. 2008-135522 A includes a MOSFET and a plurality of termination trenches provided around the MOSFET. Each of the termination trenches extends in such an annular shape as to surround a region in which the MOSFET is provided. An insulating layer is provided in each of the termination trenches. A p-type floating region is provided in a range of a semiconductor layer which is in contact with a bottom surface of each of the termination trenches. When the MOSFET is turned off, a depletion layer extends from a body region of the MOSFET toward an outer circumferential side (i.e. a region in which the termination trenches are provided). Once the depletion layer extends to the p-type floating region below an innermost termination trench, the depletion layer further extends from the p-type floating region toward the outer circumferential side. Due to this, once the depletion layer extends to an adjacent p-type floating region, the depletion layer further extends from the p-type floating region toward the outer circumferential side. Thus passing through each of the p-type floating regions, the depletion layer widely spreads around the region in which the MOSFET is provided. This allows the semiconductor device to have a higher withstand voltage.